Traditional chip cooling architectures are largely external; heat dissipation happens after it leaves the package. For the HBM memory used by AI, which vertically stacks memory chips on top of one another to improve latency and memory density, the extra heat generated has become a major design constraint.
Slated for the company’s next-generation HBM5 products due for launch from 2029 onwards, SK Hynix’s latest integrated high bandwidth memory (iHBM) takes a completely different approach of putting the cooling inside the Die-to-Die Physical Layer (D2D PHY).
This is the physical interface connecting the HBM and GPU where heat is concentrated. In iHBM this becomes a new ‘heat dissipation path’ for integrated cooling elements (ICE), reducing thermal resistance by a claimed 30%.
Not that long ago, innovations in memory and cooling would have been viewed as an interesting sideshow in a datacenter sector dominated by processor chip performance.
